The present invention relates in general to data processing systems, and in particular, to an electronic circuit having latch scan chains, as well as to a method and a system for initializing or reinitializing the electronic circuit.
The most common method for delivering test data from electronic large vector sets with corresponding long tester time and memory circuit or chip inputs to internal circuits under test and observing their outputs, is the so-called scan-design or test data register (TDR) scan chain-design. In scan-design, registers (so called flip-flops or latches) in the design are connected in one or more scan chains which are used to gain access to internal nodes of the chip. Test patterns are shifted in via these scan chain(s), functional clock signals are pulsed to test the circuit during the capture cycle, and the results are then shifted out to chip output pins and compared against the expected results or accumulated internally through some compression/signature logic.
Straightforward application of scan techniques can result in requirements. Test compression techniques address this problem, by decompressing the scan input on chip and compressing the test output. Large gains are possible since any particular test vector usually only needs to set and/or examine a small fraction of the scan chain bits.
Integrated circuits having memory arrays that are designed and manufactured with memory built-in self test (MBIST) circuitry are well-known in the art. Integrated circuits employing MBIST generally include multiple different size arrays of memory elements that require testing. Typically, during MBIST testing, a test vector is written into an array and then a read operation is performed with the results analyzed to confirm proper operation of the array under the test vector. Within a given component or section of an integrated circuit, each array of that component is conventionally tested in series in order to analyze any result of the application of the respective test vector with the respective array.
U.S. Pat. No. 8,423,846 B2 discloses an integrated circuit having an MBIST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel default initialization of the serially tested arrays. The parallel array clean up serves, inter alia, to reduce the time required to set the memory elements within the arrays to an initial state. Accordingly, this feature assists the integrated circuit to expeditiously exit a power off state with respect to the components in which it is implemented.